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ICL8048
January 2004 FN2865.3
Log Amplifier
The ICL8048 is a monolithic logarithmic amplifier capable of handling six decades of current input, or three decades of voltage input. It is fully temperature compensated and is nominally designed to provide 1V of output for each decade change of input. For increased flexibility, the scale factor, reference current and offset voltage are externally adjustable.
Features
* Full Scale Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . 0.5% * Temperature Compensated Operation . . . . . . 0oC to 70oC * Scale Factor, Adjustable . . . . . . . . . . . . . . . . 1V/Decade * Dynamic Current Range. . . . . . . . . . . . . . . . . . . . . 120dB * Dynamic Voltage Range . . . . . . . . . . . . . . . . . . . . . 60dB * Dual JFET Input Op Amps
PKG. NO.
Part Number Information
PART NUMBER ICL8048BCJE ERROR TEMPERATURE (25oC) RANGE (oC) 30mV 0 to 70 PACKAGE
Functional Diagram
ICL8048
VREF Q1 Q2 16 IREF
16 Ld CERDIP F16.3
Pinout
ICL8048 (CERDIP) TOP VIEW
VIN
fIN 2 GND 1
A1 +
+ A2
VOUT 10
-
GND IIN NC
1 2 3
16 IREF 15 GAIN 7 14 NC A2 OFFSET NULL 12 A2 OFFSET NULL 11 V+ 13 10 VOUT 9 NC A1 OUTPUT 15 GAIN
A1 OFFSET 4 NULL A1 OFFSET 5 NULL V- 6 A1 OUTPUT NC 7 8
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ICL8048
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V IIN (Input Current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2mA IREF (Reference Current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2mA Voltage Between Offset Null and V+ . . . . . . . . . . . . . . . . . . . . 0.5V Output Short Circuit Duration. . . . . . . . . . . . . . . . . . . . . . . Indefinite
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 75 22 Maximum Junction Temperature (Hermetic Package or Die) . . .175oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Die Characteristics
Number of Transistors or Gates . . . . . . . . . . . . . . . . . . . . . . . . . . 62
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER Dynamic Range IIN (1nA - 1mA) VIN (10mV - 10V) Error, % of Full Scale
VS = 15V, TA = 25oC, IREF = 1mA, Scale Factor Adjusted for 1V/Decade, Unless Otherwise Specified ICL4048BC TEST CONDITIONS RIN = 10k IIN = 1nA to 1mA TA = 0oC to 70oC, IIN = 1nA to 1mA MIN 120 60 12 10 TYP 0.20 0.60 12 36 0.8 2.5 15 250 14 13 150 5 MAX 0.5 1.25 30 75 25 200 6.7 UNITS dB dB % % mV mV mV/oC mV/V mV VRMS V V mW mA
Error, Absolute Value
IIN = 1nA to 1mA TA = 0oC to 70oC, IIN = 1nA to 1mA
Temperature Coefficient of VOUT Power Supply Rejection Ratio Offset Voltage (A1 and A2) Wideband Noise Output Voltage Swing Power Consumption Supply Current
IIN = 1nA to 1mA Referred to Output Before Nulling At Output, for IIN = 100A RL = 10k RL = 2k
Typical Performance Curves
+4 RIN = 10k +3 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) +2 +1 0 -1 -2 -3 -4 1mV 10mV 100mV INPUT VOLTAGE (V) 1V 10V IREF = 10A IREF = 100nA IREF = 1mA +8 +6 +4 +2 IREF = 1A 0 -2 -4 -6 -8 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 IREF = 1nA IREF = 1mA
INPUT CURRENT (A)
FIGURE 1. TRANSFER FUNCTION FOR VOLTAGE INPUTS
FIGURE 2. TRANSFER FUNCTION FOR CURRENT INPUTS
2
ICL8048 Typical Performance Curves
100K MAXIMUM ERROR VOLTAGE (mV) IREF = 1mA SMALL SIGNAL BANDWIDTH (Hz)
(Continued)
200 175 150 125 100 75 50 25 0 10-9 10-8 10-7 10-6 10-5 INPUT CURRENT (A) 10-4 10-3 8048BC (0oC TO 70oC)
10K
1K
100
8048BC (25oC)
10 10-11
10-9
10-7 INPUT CURRENT (A)
10-5
10-3
FIGURE 3. SMALL SIGNAL BANDWIDTH vs INPUT CURRENT
200 MAXIMUM ERROR VOLTAGE (mV) RIN = 10k 175 150 125 100 75 50 8048BC (0oC TO 70oC)
FIGURE 4. MAXIMUM ERROR VOLTAGE AT THE OUTPUT vs INPUT CURRENT
1000 434 100 VOLTAGE GAIN
log10 e VIN VOLTAGE GAIN = = VIN VOUT RIN = 10k 4343 V = /V VIN
10
1
0.1 25 0 10mV 8048BC (25oC) 100mV 1V 10V 0.01 1mV 10mV 100mV INPUT VOLTAGE (V) 1V 10V
INPUT VOLTAGE (V)
FIGURE 5. MAXIMUM ERROR VOLTAGE AT THE OUTPUT vs INPUT VOLTAGE
FIGURE 6. SMALL SIGNAL VOLTAGE GAIN vs INPUT VOLTAGE FOR RS = 10k
ICL8048 Detailed Description
The ICL8048 relies for its operation on the well known exponential relationship between the collector current and the base emitter voltage of a transistor:
qV BE I C = I S exp --------------- - 1 kT (EQ. 1)
Referring to Figure 7 it is clear that the potential at the collector of Q2 is equal to the VBE between Q1 and Q2. The output voltage is VBE multiplied by the gain of A2:
I IN R 1 + R 2 kT V OUT = -2.303 --------------------- ------ log 10 ------------R2 q I REF kT (EQ. 4)
For base emitter voltages greater than 100mV, Equation 1 becomes
qV BE I C = I S exp --------------- kT (EQ. 2)
From Equation 2, it can be shown that for two identical transistors operating at different collector currents, the VBE difference (VBE) is given by:
kT V BE = -2.303 x ------ log 10 q I C1 --------I C2 (EQ. 3)
The expression 2.303 x ------ has a numerical value of 59mV at q 25oC; thus in order to generate 1V/decade at the output, the ratio (R1 + R2)/R2 is chosen to be 16.9. For this scale factor to hold constant as a function of temperature, the (R1 + R2)/R2 term must have a 1/T characteristic to compensate for kT/q.
In the ICL8048 this is achieved by making R1 a thin film resistor, deposited on the monolithic chip. It has a nominal value of 15.9k at 25oC, and its temperature coefficient is
3
ICL8048
V+ R4 2k VREF (+15V) RREF 5 Q1 A1 + C1 150pF R0 10k R2 A1 OUTPUT GAIN 15 7 R3 Q2 + 16 R5 2k A2 R1 15.9k 10 VOUT IREF V+
IIN 2 VIN RIN 1
4
-
-
GND
680 (LOW T.C.) 1k
FIGURE 7. ICL8048 OFFSET AND SCALE FACTOR ADJUSTMENT
carefully designed to provide the necessary compensation. Resistor R2 is external and should be a low T.C. type; it should have a nominal value of 1k to provide 1V/decade, and must have an adjustment range of 20% to allow for production variations in the absolute value of R1.
The scale factor adjustment procedures outlined previously for the ICL8048, are primarily directed towards setting up 1V (VOUT) per decade (IIN or VIN) for the log amp, or one decade (VOUT) per volt (VIN) for the antilog amp. This corresponds to K = 1 in the respective transfer functions:
I IN V OUT = -K log 10 ------------I REF (EQ. 5)
ICL8048 Offset and Scale Factor Adjustment
A log amp, unlike an op amp, cannot be offset adjusted by simply grounding the input. This is because the log of zero approaches minus infinity; reducing the input current to zero starves Q1 of collector current and opens the feedback loop around A1. Instead, it is necessary to zero the offset voltage of A1 and A2 separately, and then to adjust the scale factor. Referring to Figure 7, this is done as follows: 1. Temporarily connect a 10k resistor (R0) between pins 2 and 7. With no input voltage, adjust R4 until the output of A1 (pin 7) is zero. Remove R0. Note that for a current input, this adjustment is not necessary since the offset voltage of A1 does not cause any error for current source inputs. 2. Set IIN = IREF = 1mA. Adjust R5 such that the output of A2 (pin 10) is zero. 3. Set IIN = 1A, IREF = 1mA. Adjust R2 for VOUT = 3V (for a 1V/decade scale factor) or 6V (for a 2V/decade scale factor). Step #3 determines the scale factor. Setting IIN = 1A optimizes the scale factor adjustment over a fairly wide dynamic range, from 1mA to 1nA. Clearly, if the ICL8048 is to be used for inputs which only span the range 100A to 1mA, it would be better to set IIN = 100A in Step #3. Similarly, adjustment for other scale factors would require different IIN and VOUT values.
By adjusting R2 (Figure 7) the scale factor "K" in Equation 5 can be varied. The effect of changing K is shown graphically in Figure 8 for the log amp. The nominal value of R2 required to give a specific value of K can be determined from Equation 6. It should be remembered that R1 has a 20% tolerance in absolute value, so that allowance shall be made for adjusting the nominal value of R2 by 20%.
941 R 2 = ----------------------------- ( K - 0.059 ) (EQ. 6)
ICL8048 Automatic Offset Nulling Circuit
The ICL8048 is fundamentally a logarithmic current amplifier. It can be made to act as a voltage amplifier by placing a resistor between the current input and the voltage source but, since IIN = (VIN - VOFFSET)/RIN, this conversion is accurate only when VIN is much greater than the offset voltage. A substantial reduction of VOFFSET would allow voltage operation over a 120dB range.
Applications Information
ICL8048 Scale Factor Adjustment
4
ICL8048
33k 0.1F 0V 0.1F 0.1F
1K ICL7650 +
33k 4 5
VREF (+15V)
RREF IREF
R5 2k 16 12 13
V+
Q1 RIN VIN IIN VOFFSET 2 1
Q2 R3 + ICL8048 A2 10
A1 +
VOUT
R1 15.9k A1 OUTPUT GAIN 7 15 R2 680 (LOW T.C.) 1k
C1 150pF
FIGURE 9. ICL8048 OFFSET NULLED BY ICL7650
12 IREF = 1mA OUTPUT VOLTAGE (V) 10 8 6 K=1 4 K = 0.5 2 0 -2 10-10 10-9 10-8 10-7 10-6 10-5 INPUT CURRENT (A) 10-4 10-3 K=2
Error Analysis
Performing a meaningful error analysis of a circuit containing a log and antilog amplifiers is more complex than dealing with a similar circuit involving only op amps. In this data sheet every effort has been made to simplify the analysis task, without in any way compromising the validity of the resultant numbers. The key difference in making error calculations in log/antilog amps, compared with op amps, is that the gain of the former is a function of the input signal level. Thus, it is necessary, when referring errors from output to input, or vice versa, to check the input voltage level, then determine the gain of the circuit by referring to the graphs given in the Typical Performance Curves section. The various error terms in the log amplifier, the ICL8048, are Referred To the Output (RTO) of the device. The errors are expressed in this way because in the majority of systems a number of log amps interface with an antilog amp, as shown in Figure 10.
ERROR DUE TO A (RTO) = xmV LOG AMP A ERROR DUE TO C (RTI) = zmV ANTI LOG OUTPUT AMP C
FIGURE 8. EFFECT OF VARYING "K" ON THE LOG AMPLIFIER
Figure 9 shows the ICL8048 in an automatic offset nulling configuration using the ICL7650S. The extremely low offset voltage of the ICL7650S forces its non-inverting input (and thus pin 2 of the ICL8048) to the same potential as its inverting input by nulling the first stage of the log amp. Since VOFFSET is now within a few V of ground potential, RIN can perform its voltage to current conversion much more accurately, and without an offset trimmer pot. Step 1 of the offset and scale factor adjustment is eliminated, simplifying calibration.
NOTE: The ICL7650S op amp has a maximum supply voltage of 18V. The ICL8048 will operate at this voltage, but IREF must be limited to 200A or less for proper calibration and operation. Best performance will be achieved when the ICL7650S has a 3V to 8V supply and the ICL8048 is at its recommended 15V supply. See A053 for a method of powering the ICL7650S from a 15V source.
INPUT
A LOG AMP B
INPUT
ERROR DUE TO B (RTO) = ymV
Frequency Compensation
Although the op amps in the ICL8048 are compensated for unity gain, some additional frequency compensation is required. This is because the log transistors in the feedback loop add to the loop gain. In the ICL8048, 150pF should be connected between Pins 2 and 7 (Figure 7). 5
FIGURE 10.
It is very straightforward to estimate the system error at node (A) by taking the square root of the sum-of-the-squares of the errors of each contributing block.
ICL8048
Total Error = 2 2 2 x + y + z at (A)
If required, this error can be referred to the system output through the voltage gain of the antilog circuit, using the voltage gain versus input voltage plot. The numerical values of x, y, and z in the above equation are obtained from the maximum error voltage plots. For example, with the ICL8048BC, the maximum error at the output is 30mV at 25oC. This means that the measured output will be within 30mV of the theoretical transfer function, provided the unit has been adjusted per the procedures described previously. Figure 11 illustrates this point.
8 OUTPUT VOLTAGE (V) 6 4 2 0 -2 -4 -6 -8 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 INPUT CURRENT (A) IREF = 1nA IREF = 1mA IREF = 1A TRANSFER FN 30mV THEORETICAL 30mV
Alternatively, IREF can be provided from a true current source. One method of implementing such a current source is shown in Figure 12.
+15V R1
+15V
VREF + IREF = VREF/R1 10k IREF 741 2N2609 2N2219
(TO PIN 16 ON ICL8048)
FIGURE 12.
Log of Ratio Circuit, Division
The ICL8048 may be used to generate the log of a ratio by modulating the IREF input. The transfer function remains the same, as defined by Equation 7:
I IN V OUT = - Klog 10 ------------I REF (EQ. 7)
Actual output will lie within shaded area for ICL8048BC at 25oC
FIGURE 11. TRANSFER FUNCTION FOR CURRENT INPUTS
Clearly it is possible to perform division using just one ICL8048, followed by an antilog amplifier. For multiplication, it is generally necessary to use two log amps, summing their outputs into an antilog amp. To avoid the problems caused by the IREF input not being a true virtual ground (discussed in the previous section), the circuit of Figure 12 is again recommended if the IREF input is to be modulated.
To determine the maximum error over the operating temperature range, the 0oC to 70oC absolute error values given in the table of electrical specifications should be used. For intermediate temperatures, assume a linear increase in the error between the 25oC value and the 70oC value. It is important to note that the ICL8048 requires positive values of IREF , and the input current must also be positive. Application of negative IIN to the ICL8048 or negative IREF will cause malfunction, and if maintained for long periods, would lead to device degradation. Some protection can be provided by placing a diode between pin 7 and ground.
Definition of Terms
In the definitions which follow, it will be noted that the various error terms are referred to the output of the log amp, and to the input of the antilog amp. The reason for this is explained on the previous page. Dynamic Range. The dynamic range of the ICL8048 refers to the range of input voltages or currents over which the device is guaranteed to operate. Error, Absolute Value. The absolute error is a measure of the deviation from the theoretical transfer function, after performing the offset and scale factor adjustments as outlined, (ICL8048). It is expressed in mV and referred to the linear axis of the transfer function plot. Thus, in the case of the ICL8048, it is a measure of the deviation from the theoretical output voltage for a given input current or voltage. The absolute error specification is guaranteed over the dynamic range.
Setting Up the Reference Current
The input current reference pin (IREF) is not a true virtual ground. For the ICL8048, a fraction of the output voltage is seen on Pin 16 (Figure 7). This does not constitute an appreciable error provided VREF is much greater than this voltage. A 10V or 15V reference satisfies this condition.
6
ICL8048
Error, % of Full Scale. The error as a percentage of full scale can be obtained from the following relationship:
100 x Error, absolute value Error, % of Full Scale = ---------------------------------------------------------------------Full Scale Output Voltage
Temperature Coefficient of VOUT . For the ICL8048 the temperature coefficient refers to the drift with temperature of VOUT for a constant input current. Power Supply Rejection Ratio. The ratio of the voltage change in the linear axis of the transfer function (VOUT for the ICL8048) to the change in the supply voltage, assuming that the log axis is held constant. Wideband Noise. For the ICL8048, this is the noise occurring at the output under the specified conditions. Scale Factor. For the log amp, the scale factor (K) is the voltage change at the output for a decade (i.e., 10:1) change at the input. See Equation 5.
Application Notes
For further applications assistance, see A007 "The ICL8048/8049 Monolithic Log-Antilog Amplifiers".
7
ICL8048 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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